1. Field of the Invention
The present invention relates to semiconductor package structures, and more particularly, to a chip-embedded semiconductor package being electrically connected to a second semiconductor component.
2. Description of the Prior Art
Owing to the well-developed semiconductor packaging technology, semiconductor devices nowadays come in a variety of packages. Known methods for packaging semiconductor devices involve mounting an semiconductor component on a packaging substrate or a lead frame, electrically connecting the semiconductor component to the packaging substrate or the lead frame, and encapsulating the packaging substrate with an encapsulant. Known semiconductor packages are typically modularized using multi-chip module (MCM) in order to enhance electrical functions of a semiconductor component, meet the packaging requirements for integration and miniaturization of semiconductor packages, enhance the performance and capacity of a single semiconductor package, and get in line with the trend toward miniaturization, high capacity, and high speed of electronic products. Also, multi-chip modularization downsizes semiconductor packages and enhances electrical functions thereof, and therefore has become a mainstream packaging technology. Multi-chip modularization involves mounting at least two semiconductor chips on a chip carrier of a single package, with each of the two semiconductor chips being stacked on the chip carrier, and the stack type semiconductor package is disclosed in U.S. Pat. No. 6,798,049.
Referring to FIG. 1, which is a cross-sectional view of a semiconductor package disclosed in U.S. Pat. No. 6,798,049, a semiconductor package comprises: a circuit board 10 having at least a surface with a circuit layer 11, the circuit layer 11 is disposed with a plurality of electrically conductive pads 11a and bond pads 11b, wherein an cavity 101 is formed in the circuit board 10; two semiconductor chips 121 and 122 stacked up and disposed in the opening 101; the semiconductor chips 121 and 122 being electrically connected to one another by a bonding layer 13, the semiconductor chip 122 being electrically connected to the bond pads 11b of the circuit layer 11 by conductive components 14, such as a gold wire; an encapsulant 15 for filling the cavity 101 of the circuit board 10 and encapsulating the semiconductor chips 121 and 122 and the conductive elements 14; a solder mask 16 formed on the circuit board 10 and having a plurality of openings 16a formed therein, thereby allowing the electrically conductive pads 11a to be exposed by the openings 16a; and a plurality of conductive elements 17, such as solder balls, being formed at the openings 16a of the solder mask 16 respectively, thereby finalizing the package process.
However, the semiconductor chips 121 and 122 have to be electrically connected to one another by the bonding layer 13 adapted for chip-scale connection; in other words, the semiconductor chips 121 and 122 have to undergo an electrical connection process by stacking in a fab before delivery to a packaging plant for packaging. Hence, the process is intricate and likely to incur fabrication costs.
Electrical functions and effects of modularization are enhanced by chip stacking and yet further enhancement requires additional stacking. Further stacking not only complicates the circuit layer 11 but also increases the required number of the bond pads 11b of the circuit layer 11. Given a limited or invariable available area and with the goal of package miniaturization in mind, density of circuits and quantity of the bond pads 11b cannot be increased without using a fine-pitch circuit board in carrying the semiconductor chips 121 and 122.
However, a fine pitch brings insignificant reduction in the area of a circuit board. Also, electrical functions and effect of modularization are enhanced by stacking the two semiconductor chips 121 and 122, but additional enhancement is not feasible due to the fixed number of stacked semiconductor chips.
Accordingly, an issue that faces circuit board manufacturers and calls for immediate solution involves providing a circuit board structure characterized by increased density of multi-chip modules mounted on a multilayer circuit board, reduced area for mounting the semiconductor chips on the multilayer circuit board, and a downsized package with enhanced memory capacity.